The invention relates to output buffers in integrated circuits (ICs). More particularly, the invention relates to a high-speed output buffer for an IC, the output buffer having the capability to interface with other circuits operating at various voltage levels including low voltage levels.
Integrated circuits (ICs) are growing denser and faster with every product generation. As ICs pack more and more circuitry into the same amount of silicon area and operate at higher and higher speeds, the power consumption increases rapidly. Increased power consumption is undesirable for several reasons. For example, high power consumption makes a device unsuitable for applications that run on battery power. In addition, high power consumption causes a device to give off large amounts of heat, which can be difficult and expensive to dissipate.
One method of lowering the power consumption of an IC is to decrease the operating voltage. Therefore, IC operating voltages have been steadily dropping over the years. Where once virtually all ICs operated at 5 volts, operating voltages of 3.3 volts and 2.5 volts are now common, and 1.8 volt ICs are also available. Because of this wide range of operating voltages, many ICs are designed to interface with other ICs operating at different voltage levels.
Another critical issue in today""s faster ICs is the speed at which data can be passed between different ICs. Output buffers on an IC must drive not only the capacitance of the input/output (I/O) pad, but also the capacitance of the bonding wire to the external bus, the bus wire itself, and the input buffers of the destination ICs. Therefore, the speed at which data can reliably be driven at the output pads is often the factor that determines the operating speed of an entire system.
Further, an electronic circuit operating at a lower voltage level (e.g., 1.8 volts), is inherently slower than the same electronic circuit operating at a higher voltage level (e.g., 3.3 volts or 5 volts). Hence, as operating voltages are lowered to reduce power consumption, output buffer speed becomes even more critical. Therefore, the xe2x80x9ccorexe2x80x9d (interior portion) of an IC often operates at a lower voltage level to reduce power consumption, while the I/O circuits of the IC operate at a higher voltage level to improve output performance.
Therefore, it is desirable to provide an output circuit that can accept an input signal at one voltage level (e.g., a lower voltage level) and provide an output signal at another voltage level (e.g., a higher voltage level) while maintaining a high operating speed. It is further desirable for the output circuit to be compatible with input signals arriving at the pad at a higher voltage than the operating voltage of the output circuit.
The invention provides output circuits that provide compatibility with various input and output voltage levels without sacrificing performance. A pull-up on an output terminal is gated by an internal node, and the invention encompasses various means for quickly placing a data input signal on this internal node. One embodiment includes a level shifter on the data input path, while also providing an alternative path through the output circuit that bypasses the level shifter. For example, when the input data value goes high, the alternative path quickly places an attenuated high value on the internal node, then the level shifter becomes active and xe2x80x9cboostsxe2x80x9d the voltage on the internal node to the output power high level, ensuring that the output pull-up is completely off.
An output circuit according to a first embodiment of the invention includes a level shifter that adjusts the voltage level of a first data input signal to the voltage high level of the output circuit, and provides the adjusted signal on a level shifter output node. The output circuit also includes an output terminal (which can be connected to an output pad or an I/O pad), and a pull-up and pull-down on the output terminal. The output pull-down is gated by a second data input signal that can be separate from, related to, derived from, or the same signal as the first data input signal. In one embodiment, the first and second data input signals are derived from a common data input signal.
The output circuit of the first embodiment also includes an internal node that gates the pull-up on the output terminal. The speed of this output pull-up usually determines the operating speed of the output circuit. Hence, the invention encompasses various means for quickly placing the first data input signal on the internal node driving the output pull-up.
A first path through the output circuit routes the first data input signal through a non-inverting circuit (in one embodiment comprising an inverter and two N-channel transistors) that bypasses the level shifter and places the signal onto the internal node. The first path is fast, but does not pull the internal node rail-to-rail, i.e., the internal node is not pulled all the way to the power high voltage level VDDE. Thus, a second path is also provided.
The second path through the output circuit routes the first data input signal through the level shifter to the level shifter output node. The output circuit includes a pull-up on the internal node, e.g., an N-channel transistor gated by the output node of the level shifter. A pass transistor is also provided between the internal node and the level shifter output node, gated by the signal on the output terminal. These two devices ensure that the internal node functions rail-to-rail, and therefore turns the pull-up on the output terminal completely off.
Other embodiments of the invention include one or more of the following additional circuits: a configurable slew rate control circuit; an enable circuit that configurably disables the second path through the output circuit; a high voltage tolerance circuit; an N-well control circuit; and a ground bounce current reduction circuit. In one embodiment, the output circuit forms a portion of a programmable logic device (PLD), and a slew rate configuration signal is stored in a configuration memory cell of the PLD. In another embodiment, an enable signal is similarly stored.